//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineers: Brentton Garber, Georgii Tkachuk
// 
// Create Date:    15:10:14 02/27/2013 
// Design Name: NED
// Module Name: NED 
// Project Name: Lab 1
// Target Devices: Spartan 6
// Tool versions: 
// Description: 
//
// Dependencies: none
//
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module NED(   //Port Declarations
    input i_signal,   // Signal input to be monitored
    input i_clk,      // Synchronous Clock Input
    input i_rst_b,    // An active low input which resets the logic to a default state
    output o_pulse    // A single clock wide pulse to indicate that a Positive edge has
    );           // has been detected
//------------Signal Declarations/Internal Variables-------- 
reg temp_reg_i;       // One clock shifted signal
wire d1_inv_signal_i; // One clock shifted and inverted signal
//-------------Code Starts Here--------- 
always @ (posedge i_clk or negedge i_rst_b) begin
if (i_rst_b == 1'b0) 
  temp_reg_i <= 1'b0;  
else 
  temp_reg_i <= i_signal; 
end 
assign d1_inv_signal_i = !temp_reg_i; 
assign o_pulse = !i_signal & !d1_inv_signal_i; 
endmodule